The invention relates to voltage regulator circuits for use in digital logic circuits for the purpose of reducing noise sensitivity, and in particular to voltage regulator circuits for use in clock drivers fabricated using MOS technology.
Several techniques are known in the prior art for reducing the effect of noise in a digital logic system, particularly in systems with multiphase clocking in which noise introduced by capacitive coupling is a significant problem. One technique, such as represented by Booher (U.S. Pat. No. 3,518,451), utilizes a gating system in which the outputs of each stage are isolated during certain intervals while the inherent capacitance associated with the MOS devices in each stage is charged.
Another technique is to employ additional padding capacitance in the circuit. In this technique the storage capacitance associated with the logic circuit is increased. The ratio of the noise capacitance to the total holding non-noise capacitance is increased until an acceptable level of noise is reached. The drawback of such a technique is that corresponding to the increase in capacitance is a reduction in speed of the logic circuit itself.
The problem of noise becomes even a more significant one as the supply voltage is increased. As more and more circuits are used in applications which utilize battery power supplies, the circuits are required to operate over wider voltage ranges. However, at such higher voltages the noise is also increased, increasing the likelihood of a logical error during operation. In such instances, the techniques of the prior art are not sufficient in controlling the noise, particularly in systems using multiphase clocking.